Xilinx: LIN core for FPGAs

Xilinx offers a LIN core for its FPGA families (e.g. Artic, Kintex, Virtex, and Zynq). It complies with LIN 1.3, LIN 2.1, and LIN 2.2, but not with the ISO 17987 series.

(Photo: Xilinx)

The DLIN is a soft-core compliant to the LIN physical layer. LIN is a serial communication protocol, designed for automotive applications. Compared to CAN, LIN is slower, but due to its simplicity, it is more cost effective. The offered LIN core provides an interface between a micro-controller and a LIN network. It can work as LIN master or slave node, depending on a work mode, determined by the LIN software in the micro-controller. The LIN core supports transmission speed between 1 kbit/s and 20 kbit/s. The reported information status includes the type and condition of transfer operations being performed by the LIN core, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). The product includes programmable timer, which allows detecting timeout and synchronization error. The core is described at RTL level, empowering the target use in FPGA and Asic technologies.

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